The present invention pertains to a circuit which can detect a drop in power supply voltage.
A device known as a transfer IC is usually used to establish connection between independent systems on different substrates.
Since the independent systems are operated by different power supplies, ordinarily, power to each system is turned off individually. When there is a system whose power is turned off, excess current might flow from the transfer IC of a system which is in a power-on state to the transfer IC, which has been turned off. In a worst case scenario, the transfer IC might become damaged.
In order to prevent the aforementioned damage, a power-off detection circuit has been added in the transfer IC, which was recently developed. When the power-off detection circuit detects a power-off state, the output terminal of the system will be converted to a high impedance state to prevent the flow of excess current.
Reference numeral 100 in FIG. 6 represents a conventional power-off detection circuit incorporated in a transfer IC. In said power-off detection circuit 100, the power supply voltage Vcc is divided by two resistors 101 and 102. The divided voltage is input to the gate terminal of n-channel MOS transistor 103. If the voltage obtained by dividing the power supply voltage Vcc is higher than the threshold voltage of MOS transistor 103, MOS transistor 103 is turned on. If it is lower than the threshold voltage, MOS transistor 103 is turned off.
The drain terminal of MOS transistor 103 is connected to the power supply voltage Vcc via op-amp resistor 104 and is also input to buffer circuit 105.
In this case, an inverter is used for buffer circuit 105. When the power of the system is on, MOS transistor 103 is in a power-on state. Since a LOW signal is input to buffer circuit 105, a HIGH signal will be output from buffer circuit 105.
On the other hand, when the power supply voltage Vcc drops during a power-off state, MOS transistor 103 is turned off, and a LOW signal is output from buffer circuit 105.
The output signal of buffer circuit 105 is input to output driver circuit 106. When said output driver circuit 106 detects a LOW signal, the impedance control circuit contained in output driver circuit 106 outputs a high impedance to the output terminal of the system so that no large current can flow in from other systems in the power-on state.
In recent years, however, there has been a demand to reduce the power consumption of the transfer IC or other CMOS logic ICs. The current flowing through said resistors 101 and 102 used for dividing the power supply voltage Vcc cannot be ignored.
Also, power supply voltages Vcc with various magnitudes, such as 3.3 V, 2.5 V, and 2V, have been used in recent years in order increase the speed of a system and to reduce the power consumption. Consequently, it is required that the CMOS standard logic IC be able to operate at various power supply voltages Vcc.
However, if the power supply voltage Vcc is divided as described above, operation will not be possible at a power supply voltage which is different from the assumed power supply voltage Vcc.
One aspect of the present invention is to solve the aforementioned two problems of the conventional technology by providing a power-off detection circuit that has low power consumption and is not dependent on the power supply voltage.
In accordance with an aspect of the present invention provides a power-off detection circuit comprising the following parts: a diode, which is electrically connected between first and second power supply terminals; a first capacitor, which is electrically connected between the aforementioned diode and the second power supply terminal and is charged from the first power supply terminal via the aforementioned diode; a first output transistor, which is electrically connected between the aforementioned first and second power supply terminals to output logic signals; a control transistor, which is electrically connected between the node connecting the aforementioned diode to the first capacitor and the control terminal of the aforementioned first output transistor, with its control terminal electrically connected to the aforementioned first power supply terminal; and a voltage generating circuit which is electrically connected between the node connecting the aforementioned control transistor to the control terminal of the first output transistor and the second power supply terminal.
According to another aspect of the present invention, the power-off detection circuit also has a first reset transistor, which is electrically connected between the node connecting the aforementioned diode and the first capacitor and the aforementioned second power supply terminal, and which is turned on corresponding to a reset signal to discharge the aforementioned first capacitor.
According to a further aspect of the present invention, the power-off detection circuit also has a second output transistor, which is electrically connected between the aforementioned first power supply terminal and the first output transistor and which can apply a reset signal to its control terminal.
According to yet another aspect of the present invention, in the power-off detection circuit the aforementioned voltage generating circuit is comprised of resistors. When the aforementioned control transistor becomes conductive, a prescribed voltage is supplied to the control terminal of the aforementioned first output transistor, the conductive state of the aforementioned first output transistor is changed, and the aforementioned logic signal is inverted.
According to a still further aspect of the present invention, in the power-off detection circuit the aforementioned voltage generating circuit is comprised of two capacitors which are arranged in parallel with respect to the aforementioned second capacitor, and the power-off detection circuit has a second reset transistor which is turned on corresponding to the aforementioned reset signal to discharge the second capacitor.
According to yet another aspect of the present invention, in the power-off detection circuit the aforementioned voltage generating circuit is a transistor which can form a current mirror circuit together with the aforementioned first output transistor.
According to yet another aspect of the present invention, when the power supply voltage is constantly high, the first capacitor (detecting capacitor) is charged by the power supply voltage from the first power supply terminal via the diode.
When the power supply voltage drops after the first capacitor is fully charged, since the diode is reverse-biased, there is no current flowing from the first capacitor toward the power supply voltage. Consequently, any type of diode can be used in the present invention as long as it allows charging current to flow to the first capacitor when the diode is forward-biased and cuts off the first capacitor from the power supply voltage when the diode is reverse-biased. For example, a diode-connected transistor can be used.
When the power supply voltage drops and the control transistor (starting transistor) is turned on, the first capacitor is connected to the voltage generating circuit, and a discharge current is supplied via the control transistor.
The voltage generating circuit generates a voltage depending on the supplied discharging current and outputs the voltage to the first output transistor. The on/off state of the first output transistor is reversed by the voltage. That is, if the output transistor is off with the power supply voltage in a constantly high state, it will be turned on. On the other hand, if the output transistor is on, it will be turned off. Consequently, other circuits can detect a drop in the power supply voltage depending on the output signal (logic signal) of the output transistor.